5-Bit PLC SSDs will not arrive until 2025, according to Western Digital

SLC, MLC, TLC, QLC and now PLC: the waltz of NAND Flash memories continues.

Within a few years, the type of memory cells used in SSDs has evolved considerably. The next step is called DFC, but in the opinion of Western Digital, we will have to wait a little longer.

Capacity up 25%

SLC stands for single-level cell or single-level cell. The principle is simple: you can store 1 bit of information per cell. Very quickly, however, MLC, or multi-level cell, appeared to significantly improve storage capacities.

Thus, the first MLC allowed, by storing 2 bits per cell, to double the capacities. The transition to TLC resulted in an additional 50% capacity gain with 3 bits per cell storage. We then had +33% capacity via the QLC and we expect +25% with the PLC.

A very logical evolution, since the PLC (for penta-level cell) allows to store 5 bits of information per cell. Currently, this technology is still under development, and if Intel or Toshiba are optimistic, Western Digital is less optimistic.

An even more sacrificed endurance?

To evolve towards the PLC, it is indeed necessary that the NAND Flash is perfectly operational of course, but also that controllers are able to manage it effectively. This is exactly where the problem lies for Western Digital.

The American believes that the first controllers, and therefore the first SSD units, will not be available for mass production until 2025. The future will tell us who will be right, but we hope that this period of time will allow us to advance the endurance of the cells

Indeed, by increasing the amount of bits stored per cell, the MLC, TLC, QLC and now PLC have, each time, reduced the endurance of the NAND Flash. The graph above illustrates the phenomenon and the problem it could pose in the near future.

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