the Emotion Engine

The heart of the PS2 is a 64-bit Toshiba MIPS processor dubbed the Emotion Engine, or EE.
The EE is the predecessor of ArTile Micro’s TX79 line of System-on-a-Chip (SoC) processors.A SoC design is one in which all of the external peripherals required to manage the system are integrated onto a single chip. For example, a common TX79 chip, the TMPR7901, integrates the MIPS CPU core, an SDRAM memory controller, a PCI bus controller, and an Ethernet controller,among other peripherals.The main benefits of SoC processors are reduced manufacturing costs and better performance between the integrated peripherals. SoC designs usually contain one or more high-speed internal buses that interface with external peripherals using a slower, shared system bus.

The EE includes the following documented on-chip peripherals:
■ MIPS R5900 CPU core
■ Two vector processing units (VUs or VPUs)
■ Floating point unit (FPU)
■ DMA controller (DMAC)
■ Interrupt controller (INTC)
■ Programmable timers
■ Sub-CPU interface (SIF)
■ Two VU interfaces (VIFs)
■ Graphics Synthesizer (GS) interface (GIF)
■ Image processing unit (IPU)
It also includes the following undocumented peripherals:
■ RDRAM controller (RDRAMC)
■ Serial I/O port (SIO; UART)
■ JTAG (IEEE 1149.1) Boundary-Scan Interface

The Serial I/O Port
The SIO implements a high-speed UART with an 8-byte transmit first in, first out (FIFO) and 16-byte receive FIFO. It also includes the common CTS and RTS signals for hardware-based flow control.Although the SIO-related pins are unconnected in consumer PS2s, the EE’s BIOS and runtime kernel use the SIO to output status messages during the PS2 boot process.

The SIO isn’t documented in the EE User’s Manual, so I had a look in the PS2’s BIOS for the initialization and character output code. I also found a wealth of information on the SIO interrupt and hardware registers in the Toshiba TX79 core Architecture Manual, the TMPR7901 hardware
manual, and the TMPR4925 hardware manual. It turns out that the TX79 Core Architecture Manual is nearly identical to Sony’s EE Core User’s Manual, except that all SIO-related documentation was removed from the latter.
After studying the BIOS and kernel SIO code, reading the available documentation, and writing a few test programs, I was able to assemble a reasonably accurate list of registers and definitions.The EE’s SIO shares most of its registers with the TX79 core implementation, but I couldn’t find any indication that DMA was supported. It also shares a few register definitions with the TX7901’s UARTs.

shows the SIO register map.

rupt status register to determine the cause of the interrupt.The EE kernel uses the SIO exception as a
means to start the kernel’s built-in debugger.
To initialize the SIO, you first write a value to SIO_LCR indicating the number of data bits and stop
bits and whether to enable parity checking.You can also specify where the baud rate generator will get
the clock source used to determine the baud rate.The next step is to reset both FIFOs and to optionally
enable any interrupts. Finally, you need to calculate the divisor and the clock value used to maintain the
baud rate.The code in Figure 4.22 is an example of how to initialize the SIO with the specified baud
rate, using the standard transmission parameters of 8N1 (8 data bits, no parity checking, 1 stop bit).

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